1. Field of the Invention
This invention relates to circuit design methods and tools.
2. Description of Related Art
As it has become possible to integrate more circuit elements onto a single chip, it has also become desirable to design circuits, particularly digital circuits, with more elements. Circuits with more elements are often more complex and perform more functions than earlier circuits, or perform the same functions as earlier circuits but with more data at once. As circuits have become more complex, quickly designing circuits which are simultaneously fast and compact has become more difficult. Accordingly, it is now common to employ automated circuit design tools which allow the tool user to specify a circuit design and which compile that circuit design into a netlist for fabrication. Many automated circuit design tools further attempt to optimize the netlist for speed, area, or other design parameters.
One problem which has arisen in the art is that, due to the large number of circuit elements, the number of possible optimizations rises exponentially with the number of gates in the circuit. Required computation time and storage therefore also rise exponentially, causing it to be difficult to automatically prepare a circuit which is larger than about 5,000 gates (although the threshold at which difficulty becomes insurmountable varies significantly with the complexity of the circuit). Moreover, automated design runs for circuits of this level of complexity can occupy between about six to nine hours of computation on an individual workstation.
However, tool users often wish to design circuits which have 100,000 gates or more, using automated design tools. One known method for designing such circuits is to partition the circuit into segments which are each within the size limit of the design tool, to use the design tool to optimize each segment, and to combine the segments together into a consolidated circuit. While this method achieves the goal of designing relatively complex or large circuits, it has serious drawbacks. First, the tool user is forced to partition the circuit into segments before knowing how that partition will affect the optimization of the circuit. Second, the tool user is forced to optimize each segment individually using the design tool, rather than being able to optimize across segments. The tool user may be required to engage in painstaking reoptimization of each segment of the circuit in an effort to obtain the preferred tradeoff of speed and area for the entire circuit.
Accordingly, it would be advantageous to provide an improved circuit design tool which allows the tool user to quickly design and antomatically optimize complex or large circuits.
The following patents and publications may be pertinent:
U.S. Defensive Publication T 938,005, published Sep. 2, 1975, titled "Process for Making LSI Chips Having Both Rules Driven and Free Form Design"; PA0 U.S. Defensive Publication T 940,020, published Nov. 4, 1975, titled "Automatic Circuit Generation Process and Apparatus"; PA0 U.S. Pat. No. 3,968,478, issued Jul. 6, 1976, in the name of inventor William D. Mensch, Jr., titled "Chip Topography for MOS Interface Circuit"; PA0 U.S. Pat. No. 4,093,990, issued Jun. 6, 1978, in the name of inventors Konrad Koller, et al., titled "Method for the Production of Mask Patterns for Integrated Semiconductor Circuits"; PA0 U.S. Pat. No. 4,377,849, issued Mar. 22, 1983, in the name of inventors William C. Finger, et al., titled "Macro Assembler Process for Automated Circuit Design"; PA0 U.S. Pat. No. 4,652,992, issued Mar. 24, 1987, in the name of inventor William D. Mensch, Jr., titled "Topography of Integrated Circuit CMOS Microprocessor Chip"; PA0 U.S. Pat. No. 4,701,860, issued Oct. 20, 1987, in the name of inventor James M. Mader, titled "Integrated Circuit Architecture Formed of Parametric Macro-Cells"; PA0 U.S. Pat. No. 4,827,428, issued May 2, 1989, in the name of inventors Alfred E. Dunlop, et al., titled "Transistor Sizing System for Integrated Circuits"; PA0 U.S. Pat. No. 4,829,446, issued May 9, 1989, in the name of inventor Marlow R. Draney, titled "Method and Apparatus for Recording and Rearranging Representations of Objects in a Model of a Group of Objects Located Using a Co-Ordinate System"; PA0 U.S. Pat. No. 5,068,823, issued Nov. 26, 1991, in the name of inventor Jeffrey I. Robinson, titled "Programmable Integrated Circuit Using Topological and Parametric Data to Selectively Connect and Configure Different High Level Functional Blocks Thereof"; PA0 U.S. Pat. No. 5,119,314, issued Jun. 2, 1992, in the name of inventors Takashi Hotta, et al., titled "Semiconductor Integrated Circuit Device"; PA0 U.S. Pat. No. 5,175,693, issued Dec. 29, 1992, in the name of inventors Sachiko Kurosawa, et al., title "Method of Designing Semiconductors Integrated Circuit Device"; PA0 U.S. Pat. No. 5,282,140, issued Jan. 25, 1994, in the name of inventors Satoshi Tazawa, et al., titled "Particle Flux Shadowing for Three-Dimensional Topography Simulation"; PA0 U.S. Pat. No. 5,297,053, issued Mar. 22, 1994, in the name of inventors Mark D. Pease, et al., titled "Method and Apparatus for Deferred Package Assignment for Components of an Electronic Circuit for a Printed Circuit Board"; and PA0 U.S. Pat. No. 5,319,570, issued Jun. 7, 1994, in the name of inventors Joanne M. Davidson, et al., titled "Control of Large Scale Topography on Silicon Wafers".
The pertinence of the related art will also be apparent to those skilled in the art after perusal of this application.